Car and Stuff
I'm grumpy. My car won't start. I've been working on it all day.

The problem is that it's flooded and it's a fuel-injected engine. You're not meant to be able to flood a fuel-injected engine. If however, you drive my car a very short distance (<100m) and turn it off it can get into this flooded state. It seems that the petrol burns off the oil in the cylinder, and if you don't keep driving until the engine has warmed up the oil doesn't get pumped back into the cylinders. Then when you next go to start it you don't have enough compression, and the ECU pumps lots of petrol in, causing the flood.

So the problem is that you have to get the petrol out of the cylinders. To do this you pull the fuse (or, in my case the relay) for the fuel injection system, then turn the car over for a while. It seems that in my case "a while" is a full 90 seconds, at least.

But you can't really turn the engine over for more than about 30 seconds without risking overheating the starter motor. So you have to do it in stages. Because I've been fucking around with it all day, and then my folks showed up with their own bright ideas, the battery is right down. So I have to charge it up enough to turn it over, pump out the petrol, repeat until all the petrol is gone.

I've tried a few things to shortcut this process. I've tried taking the spark plugs out and turning the engine over to pump out the petrol that way. I did this for an hour or so with no damn luck. I've drained the oil and put in new oil only a little above the empty point, reasoning that if I'm down on oil there'll be less backpressure.

There's a procedure in the manual that says to try holding the accelerator flat down and turning over for 15 seconds. This is typically the exact wrong thing to be doing with a flooded engine. I figure this is meant to be sensed by the computer and it'll run its little "starting with flooded engine" programme, but it doesn't seem to work.

So I've put new spark plugs in, figuring maybe the spark was a bit weak.

But the fucking thing still won't start. And I'm grumpy about it. These computerised, fuel-injected engines are great when they're working but are a mighty pain in the arse when they're not.


I think I'm back on the FPGA kool-ade. I'd heard about them and knew basically what they were good for before going into my thesis last year. They sounded cool so I wanted to play with them. Trying to jump right in implementing something quite complicated, even if I did have a year to putter away at it, left me rather disenfranchised. I hadn't anticipated how easily you can get mired in timing issues, how much work serialising or de-serialising data is, and how astonishingly bad the tools are.

And the tools really are bad. They're buggy, slow as all hell and the interface of these things seems to have come from darkest realms of VisualBasic.

It seems to me that there's a need for a HDL gcc - an open source compiler to come along and basically become much better than the vendor-supplied compilers. The problem is with the format of the bitstream that configures the FPGA (the stage at the end, after compiling the HDL to a netlist and then working out the placement and routing for that netlist) The vendors are trying to keep this format secret.

This semester one of my units involved a lot of FPGA work and I've started to come around. The unit was about embedded real time systems, and much of it was about connecting and comparing HDL solutions to a problem with microcontroller-based solutions (using a soft core and a RTOS). In working through the labs and the assignments I got quite a bit better at Verilog and was even now and then surprised at things being much easier than expected. (E.g. I was happy to find Verilog has an integer divide - though it's unsigned. It must generate a boat load of logic, though.)

So there was some strange lump I had to get over that I hadn't hit with my thesis. Once I passed an invisible point in accumulating Verilog knowledge it all just came together. Even things I had always thought of as highly sequential and therefore best suited to a microcontroller started to make sense in little state machines on the FPGA. Still, it'd be nice to see support for floating point arithmetic and a few other bits and pieces in HDL. It seems to me that there are many problems that currently call for a DSP that would be better done by an FPGA. Adding signal processing extensions to FPGAs makes more sense to me than adding memory and arithmetic operations to a CPU and calling it a DSP. Certainly when I look at SDR-type projects the FPGA seems fantastically applicable.

So now I find myself looking at the Cell CPU and considering the programming possibilities. I think we've got a long way to go with our approaches to programming for these architectures, but I'm excited by some of the work done with LLVM that takes a program, analyses it and compiles parts of it to a sequential program for a CPU and other parts to HDL. I wonder how much you could get out of a PS3 if you wrote a back-end to LLVM that analyses the IR and splits it off into threads for each of the Cell's SPUs.

Clearly it's exam period because my mind is wandering.

This is so good it makes me want to vote for the guy:
http://vimeo.com/1891426?pg=embed&sec=1891426

Obama '08 - Vote For Hope from MC Yogi on Vimeo.